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author | Andreas Baumann <mail@andreasbaumann.cc> | 2021-11-14 18:45:26 +0100 |
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committer | Andreas Baumann <mail@andreasbaumann.cc> | 2021-11-14 18:45:26 +0100 |
commit | 990b229364cf9eaf401ee17cbd8d6c4981d522eb (patch) | |
tree | e55e83b315256a771f51908cf0ec0c95f87d6fcf /extra/llvm12/disable-bswap-for-spir.patch | |
parent | c205ac4aa24e1241bf2905aa82ffe600502a59e6 (diff) |
-rw-r--r-- | extra/llvm12/disable-bswap-for-spir.patch | 50 |
diff --git a/extra/llvm12/disable-bswap-for-spir.patch b/extra/llvm12/disable-bswap-for-spir.patch new file mode 100644 index 00000000..11385011 --- /dev/null +++ b/extra/llvm12/disable-bswap-for-spir.patch @@ -0,0 +1,50 @@ +# Based on https://github.com/ispc/ispc/blob/main/llvm_patches/12_0_disable-A-B-A-B-and-BSWAP-in-InstCombine.patch + +diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp +index d01a021bf3f4..bccce825a03d 100644 +--- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp ++++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp +@@ -15,6 +15,7 @@ + #include "llvm/ADT/APInt.h" + #include "llvm/ADT/STLExtras.h" + #include "llvm/ADT/SmallVector.h" ++#include "llvm/ADT/Triple.h" + #include "llvm/Analysis/InstructionSimplify.h" + #include "llvm/Analysis/ValueTracking.h" + #include "llvm/IR/Constant.h" +@@ -1369,9 +1370,12 @@ Instruction *InstCombinerImpl::visitAdd(BinaryOperator &I) { + } + } + +- // A+B --> A|B iff A and B have no bits set in common. +- if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT)) +- return BinaryOperator::CreateOr(LHS, RHS); ++ // Disable this transformation for ISPC SPIR-V ++ if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) { ++ // A+B --> A|B iff A and B have no bits set in common. ++ if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT)) ++ return BinaryOperator::CreateOr(LHS, RHS); ++ } + + // add (select X 0 (sub n A)) A --> select X A n + { +diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +index 120852c44474..8de55311ce3e 100644 +--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp ++++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +@@ -2671,9 +2671,12 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) { + if (Instruction *FoldedLogic = foldBinOpIntoSelectOrPhi(I)) + return FoldedLogic; + +- if (Instruction *BitOp = matchBSwapOrBitReverse(I, /*MatchBSwaps*/ true, +- /*MatchBitReversals*/ true)) +- return BitOp; ++ // Disable this transformation for ISPC SPIR-V ++ if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) { ++ if (Instruction *BitOp = matchBSwapOrBitReverse(I, /*MatchBSwaps*/ true, ++ /*MatchBitReversals*/ true)) ++ return BitOp; ++ } + + if (Instruction *Funnel = matchFunnelShift(I, *this)) + return Funnel; |